Typically, a computer system includes a number of integrated circuit chips that communicate with one another to perform system applications. As chip speeds increase, the amount of data communicated between chips increases to meet the demands of some system applications. Other system applications do not need the increased chip speeds and bandwidth or the systems have limited power resources. In these systems, the chips can operate at slower speeds and lower power levels. In other systems, applications are being developed to take advantage of a dynamic frequency change environment. In the dynamic frequency change environment, the operational frequency of at least some of the chips can be changed from one frequency to any other frequency within a specified frequency range.
Often, the computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The RAM chips can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), reduced latency DRAM (RLDRAM), pseudo static RAM (PSRAM), and low power DDR-SDRAM (LPDDR-SDRAM).
Sometimes, data and a strobe signal are communicated between chips, such as a controller and a RAM, via a communications link to read and write data. The RAM receives an external clock signal and provides an internal clock signal based on the received external clock signal. To write data from the controller to the RAM, data and a strobe signal are transmitted to the RAM and the received data is sampled via the received strobe signal. The RAM clocks the received data into the chip via the internal clock signal. To read data from the RAM, output data and strobe signals are transmitted from the RAM. The output data and strobe signals are aligned with the external clock signal via the internal clock signal. The internal clock signal can be locked to the external clock signal and track the external clock signal frequency via a delay locked loop (DLL).
In a dynamic frequency change environment, the controller may slowly change the frequency of the external clock signal from one frequency to any other frequency within the frequency range of the dynamic frequency change environment. The frequency of the external clock signal gradually changes from one frequency to another frequency over many clock cycles, such as thousands of clock cycles or millions of clock cycles.
Typically, a DLL in the RAM receives the external clock signal and locks onto the external clock signal to produce the internal clock signal. The internal clock signal is used internally and to provide output data and strobe signals aligned with the external clock signal. The DLL is reset to lock onto the external clock signal within a specified number of clock cycles, such as 300 or 500 clock cycles, of the external clock signal. The DLL tracks frequency changes of the external clock signal within a limited frequency range that is less than the frequency range of the dynamic frequency change environment. However, the DLL must be reset to lock onto the external clock signal beyond the limited frequency range. Resetting the DLL and locking onto the external clock signal disrupts operation of the RAM and the system.
For these and other reasons there is a need for the present invention.